TINI Memory Map

CE address space spans from 0 - 4MB. 0x00000000 - 0x003FFFFF
PCE address space spans from 8MB - 12MB. 0x00800000 - 0x00BFFFFF

Here's a memory/address map:

Address (hex): Chip Enable: Contents:
000000 - 07FFFF *CE0 Flash ROM (on-board, 512K)
080000 - 0FFFFF *CE0 Image of Flash ROM (or off-board 512K Flash ROM on Socket board)
     
100000 - 17FFFF *CE1 Image of SRAM0 (512K)
180000 - 1FFFFF *CE1 SRAM0 (512K)
     
200000 - 27FFFF *CE2 SRAM1 (512K)
280000 - 2FFFFF *CE2 Image of SRAM1 (512K)
     
300000 - 307FFF *CE3 SMC Ethernet Controller
308000 - 30FFFF *CE3 Available Peripheral CODE & DATA Space (32K)
310000 - 31FFFF *CE3 Real Time Clock
320000 - 38FFFF *CE3 Available Peripheral CODE & DATA Space (896K)
     
000000 - 0FFFFF *PCE0 Off-board RAM or Peripheral space (1 meg)
100000 - 1FFFFF *PCE1 Off-board RAM or Peripheral space (1 meg)
200000 - 2FFFFF *PCE2 Off-board RAM or Peripheral space (1 meg)
300000 - 3FFFFF *PCE3 Off-board RAM or Peripheral space (1 meg)


Socket Board *CE3 Peripheral Decoding (Binary):
A23 <--------------------------------> A0  
0011 10X0 XXXX XXXX 000X 0X10 Write strobes only, LCD Control Write
0011 10X0 XXXX XXXX 000X 1X10 Write strobes only, LCD Data Write
0011 10X0 XXXX XXXX 000X 0X00 Write strobes only, Parallel I/O lines ODB0-ODB7
0011 10X0 XXXX XXXX 000X 0X01 Write strobes only, Parallel I/O lines OCB0-OCB7
0011 10X0 XXXX XXXX 000X 0X00 Read strobes only, Parallel I/O lines IDB0-IDB7
0011 10X0 XXXX XXXX 000X 0X01 Read strobes only, Parallel I/O lines ICB0-ICB7
0011 10X0 XXXX XXXX 001X XXXX P16552D Dual UART Access Read/Write

Under program control, each *CE segment can be either CODE & DATA space or just CODE ONLY space. When any *CEn segment is designated as CODE ONLY space, the corresponding *PCEn segment is enabled to be data. This means that code cannot be executed from any *PCE segment.

NOTE: To allow the on-board Flash ROM to be supplanted for first-birthday initialization and other special applications, the *CE0 line is not connected to the Flash ROM on the TINI board. An external connection is required to connect *CE0 to *RCE0 (the Flash ROM) for proper operation of the TINI module.